AD14060L datasheet(3/48 Pages) AD

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AD14060/AD14060L

Rev. B | Page 3 of 48

SPECIFICATIONS

Table 1. Recommended Operating Conditions

B Grade

K Grade

Parameter

Min

Max

Min

Max

Unit

VDD

Supply Voltage (5 V)

4.75

5.25

4.75

5.25

Supply Voltage (3.3 V)

3.15

3.6

3.15

3.6

TCASE

Case Operating Temperature

−40

+100

+85

°C

ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)

Table 2.

5 V

3.3 V

Parameter

Case

Temp

Test

Level

Test Condition

Min

Typ

Max

Min

Typ

Max

Unit

VIH1

High Level Input Voltage1

Full

@ VDD = max

2.0

VDD + 0.5

2.0

VDD + 0.5

VIH2

High Level Input Voltage2

Full

@ VDD = max

2.2

VDD + 0.5

2.2

VDD + 0.5

VIL

Low Level Input Voltage1, 2

Full

@ VDD = min

0.8

VOH

High Level Output Voltage3, 4

Full

@ VDD = min, IOH = −2.0 mA

4.1

2.4

VOL

Low Level Output Voltage3, 4

Full

@ VDD = min, IOL = 4.0 mA

0.4

IIH

High Level Input Current5, ,6 7

Full

@ VDD = max, VIN = VDD max

µA

IIL

Low Level Input Current5

Full

@ VDD = max, VIN = 0 V

µA

IILP

Low Level Input Current6

Full

@ VDD = max, VIN = 0 V

150

µA

IILPX4

Low Level Input Current7

Full

@ VDD = max, VIN = 0 V

600

µA

IOZH

Three-State Leakage Current8, , ,

9 10 11

Full

@ VDD = max, VIN = VDD max

µA

IOZL

Three-State Leakage Current8, 12

Full

@ VDD = max, VIN = 0 V

µA

IOZHP

Three-State Leakage Current12

Full

@ VDD = max, VIN = VDD max

350

µA

IOZLC

Three-State Leakage Current13

Full

@ VDD = max, VIN = 0 V

1.5

IOZLA

Three-State Leakage Current14

Full

@ VDD = max,

VIN = 1.5 V (5 V), 2 V (3.3 V)

350

µA

IOZLAR

Three-State Leakage Current10

Full

@ VDD = max, VIN = 0 V

4.2

IOZLS

Three-State Leakage Current9

Full

@ VDD = max, VIN = 0 V

150

µA

IOZLSX4

Three-State Leakage Current11

Full

@ VDD = max, VIN = 0 V

600

µA

IDDIN

Supply Current (Internal)15

Full

tCK = 25 ns, VDD = max

1.4

2.92

1.0

2.2

IDDIDLE

Supply Current (Idle)16

Full

VDD = max

800

760

CIN

Input Capacitance17, 18

25°C

1 Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, STBS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2, BR6-1, RPBA, CPAy, TFS0,

TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0,

RCLKy1.

2 Applies to input pins: CLKIN, RESET, TRST.

3 Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG, REDY, DMAG1, DMAG2,

BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU.

4 See the

section for typical drive current capabilities.

Output Drive Currents

5 Applies to input pins: STBS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.

6 Applies to input pins with internal pull-ups: DR0, DRy1, TDI.

7 Applies to bused input pins with internal pull-ups: TRST, TMS.

8 Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2, BMSA, BMSBCD, TDO,

EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is not requesting bus

mastership. HBG and EMU are not tested for leakage current.)

9 Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.

10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another

ADSP-2106x is not requesting bus mastership.)

11 Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.

12 Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.

13 Applies to CPAy pin.

14 Applies to ACK pin, when the keeper latch is enabled.

15 Applies to VDD pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each

internal memory block, and one DMA transfer is occurring from/to internal memory at tCK = 25 ns.

16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.

17 Applies to all signal pins.

18 Guaranteed, but not tested.

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