AD14060L datasheet(18/48 Pages) AD

18 / 48 page

AD14060/AD14060L

Rev. B | Page 18 of 48

DMA HANDSHAKE

These specifications describe the three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For handshake

mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the

ADDR31-0, RD, WR, SW, PAGE, MS3-0, ACK, and DMAG signals. For paced master mode, the data transfer is controlled by ADDR31-0, RD,

WR, MS3-0, and ACK (not DMAG). For paced master mode, the memory read—bus master, memory write—bus master, and synchronous

read/write—bus master timing specifications for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.

Table 15. Specifications

5 V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

tSDRLC

DMARx Low Setup before CLKIN1

tSDRHC

DMARx High Setup before CLKIN1

tWDR

DMARx Width Low (Nonsynchronous)

tSDATDGL

Data Setup after DMAGx Low2

9 + 5 DT/8

tHDATIDG

Data Hold after DMAGx High

tDATDRH

Data Valid after DMAGx High2

15.5 + 7 DT/8

tDMARLL

DMAGx Low Edge to Low Edge

23 + 7 DT/8

tDMARH

DMAGx Width High

Switching Characteristics:

tDDGL

DMAGx Low Delay after CLKIN

9 + DT/4

16 + DT/4

9 + DT/4

16 + DT/4

tWDGH

DMAGx High Width

6 + 3 DT/8

tWDGL

DMAGx Low Width

12 + 5 DT/8

tHDGC

DMAGx High Delay after CLKIN

−2 − DT/8

+7 − DT/8

−2 − DT/8

+7 − DT/8

tVDATDGH

Data Valid before DMAGx High3

7.5 + 9 DT/16

tDATRDGH

Data Disable after DMAGx High4

−1

+7.5

−1

+7.5

tDGWRL

WR Low before DMAGx Low

−0.5

+2.5

−0.75

+2.5

tDGWRH

DMAGx Low before WR High

9.5 + 5 DT/8 + W

tDGWRR

WR High before DMAGx High

0.5 + DT/16

3.5 + DT/16

0.5 + DT/16

3.5 + DT/16

tDGRDL

RD Low before DMAGx Low

−0.25

+2.5

2.5

tDRDGH

RD Low before DMAGx High

11 + 9 DT/16 + W

tDGRDR

RD High before DMAGx High

3.5

tDGWR

DMAGx High to WR, RD, DMAGx Low

4.5 + 3 DT/8 + HI

tDADGH

Address/Select Valid to DMAGx High

16 + DT

tDDGHA

Address/Select Hold after DMAGx High

−1.5

W = number of wait states specified in WAIT register × tCK.

HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.

1 Required only for recognition in the current cycle.

2 tSDATDGL is the data setup requirement, if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data

can be driven tDATDRH after DMARx is brought high.

3 tVDATDGH is valid, if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 7.5 + 9 DT/16 + (n × tCK), where n

equals the number of extra cycles that the access is prolonged.

4 See the

section for the calculation of hold times given capacitive and dc loads.

System Hold Time Calculation Example

AD14060L Datasheet(PDF) 18 Page - Analog Devices

AD14060L Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL