AD14060/AD14060L

Rev. B | Page 13 of 48

MULTIPROCESSOR BUS REQUEST AND HOST BUS REQUEST

Use these specifications for passing of the bus mastership among multiprocessing ADSP-2106xs (BRx) or a host processor (HBR, HBG).

Table 12. Specifications

5 V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

HBG Low to RD/WR/CS Valid1

19.5 + 5 DT/4

19.5 + 5 DT/4

ns

HBR Setup before CLKIN2

20 + 3 DT/4

20 + 3 DT/4

ns

HBR Hold before CLKIN2

13.5 + 3 DT/4

13.5 + 3 DT/4

ns

HBG Setup before CLKIN

13 + DT/2

13 + DT/2

ns

HBG Hold before CLKIN High

5.5 + DT/2

5.5 + DT/2

ns

BRx, CPA Setup before CLKIN3

13 + DT/2

13 + DT/2

ns

BRx, CPA Hold before CLKIN High

5.5 + DT/2

5.5 + DT/2

ns

RPBA Setup before CLKIN

21 + 3 DT/4

21 + 3 DT/4

ns

RPBA Hold before CLKIN

11.5 + 3 DT/4

11.5 + 3 DT/4

ns

Switching Characteristics:

HBG Delay after CLKIN

8 − DT/8

8 − DT/8

ns

HBG Hold after CLKIN

−2 − DT/8

−2 − DT/8

ns

BRx Delay after CLKIN

8 − DT/8

8 − DT/8

ns

BRx Hold after CLKIN

−2 − DT/8

−2 − DT/8

ns

CPA Low Delay after CLKIN

9 − DT/8

9.5 − DT/8

ns

CPA Disable after CLKIN

–2 − DT/8

+5.5 − DT/8

−2 − DT/8

+5.5 − DT/8

ns

REDY (O/D) or (A/D) Low from CS and HBR Low4

9.5

12

ns

REDY (O/D) Disable or REDY (A/D) High from HBG4

40 + 27 DT/16

40 + 27 DT/16

ns

REDY (A/D) Disable from CS or HBR High4

11

11

ns

easily accomplished by driving an upper address signal high when HBG is asserted.