AD14060L datasheet(2/48 Pages) AD

2 / 48 page

AD14060/AD14060L

Rev. B | Page 2 of 48

TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics (3.3 V, 5 V Supply)............................ 3

Explanation of Test Levels........................................................... 4

Timing Specifications....................................................................... 5

Memory Read—Bus Master........................................................ 8

Memory Write—Bus Master ....................................................... 9

Synchronous Read/Write—Bus Master................................... 10

Synchronous Read/Write—Bus Slave ...................................... 12

Multiprocessor Bus Request and Host Bus Request .............. 13

Asynchronous Read/Write—Host to AD14060/AD14060L.15

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS ..... 17

DMA Handshake........................................................................ 18

Absolute Maximum Ratings.......................................................... 27

ESD Caution................................................................................ 27

Pin Configuration and Function Descriptions........................... 28

Pin Function Descriptions ........................................................ 30

Detailed Description ...................................................................... 34

Architectural Features................................................................ 34

Shared Memory Multiprocessing ............................................. 34

Off-Module Memory and Peripherals Interface .................... 36

Link Port I/O............................................................................... 38

Serial Ports .................................................................................. 38

Program Booting ........................................................................ 38

Host Processor Interface ........................................................... 39

Direct Memory Access (DMA) Controller ............................. 39

Applications..................................................................................... 40

Development Tools .................................................................... 40

Quad-SHARC Development Board......................................... 40

Other Package Details................................................................ 40

Target Board Connector for Emulator Probe......................... 40

Output Drive Currents .............................................................. 42

Power Dissipation ...................................................................... 42

Test Conditions........................................................................... 43

Assembly Recommendations.................................................... 45

PCB Layout Guidelines.............................................................. 46

Mechanical Characteristics ....................................................... 47

Additional Information ............................................................. 47

Outline Dimensions ....................................................................... 48

Ordering Guide .......................................................................... 48

REVISION HISTORY

12/04—Rev. A to Rev. B

Format Updated..................................................................Universal

Changes to Specifications Section .................................................. 3

Changes to Development Tools Section ...................................... 40

Changes to Target Board for Emulator Probe Section .............. 40

Changes to Figure 27...................................................................... 42

Updated Outline Dimensions ....................................................... 48

Changes to Ordering Guide .......................................................... 48

10/97—Rev. 0 to Rev. A

4/97—Revision 0: Initial Version

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