2-24

a higher ripple voltage for load current between 0.2A and

0.6A. If the load is sensitive to power supply ripple during this

load range, the lower efficiency HMI setting should be used.

The voltage on the HMI pin is used to clamp the lower limit of

error amplifier output voltage and the minimum peak

inductor current. This voltage is set by a 20

µA current source

and the resistor, R4.

Soft-Start

Set the Soft-Start capacitor, C8 so that the output voltage

ramps to its final value with a current between the hysteretic

mode current and the rated current. The minimum value for

C8 can be determined from:

Bypass and Filter Capacitors

Capacitor C12 supplies the leading edge PWM current each

switching cycle. A high quality (X7R dielectric ceramic)

0.1

µF surface-mount capacitor is recommended. Locate

C12 directly across the VIN and PGND pins.

dielectric ceramic) surface-mount capacitor (C4). Locate C4

directly across the VCC and GND pins.

The value for capacitor C5 should be selected as described in

the Charge Pump Regulator above. A single high quality (X7R

dielectric ceramic) capacitor is usually adequate. Some

applications may need a high capacitance, electrolytic for

charge-pump operation. For these applications, a high quality

capacitor in parallel with the electrolytic is recommended.

Locate C5 directly across the CP+ and CP- pins.

the reference and hysteretic comparator functions. A 2k

Ω

resistor for R5 and a 0.1

µF Capacitor for C10 is recommended.

Locate C10 directly across the VINF and GND pins.

Thermal Design

The power ground (PGND) pins of the SOIC package

provide a thermal conduction path for removing heat from

the HIP5020. Inside the package, the HIP5020 die is

mounted on a copper structure with connections to PGND

(pins 6, 7, 8, 9, 20, 21, 22, and 23). Solder the SOIC to a

circuit board with a copper ground plane to remove heat

from the package. With good component layout and 3

square inches of copper ground plane, the junction-to-

converter’s power dissipation will be in the HIP5020 and the

output inductor, L1. The power dissipated in the HIP5020

can be estimated from the converter’s full load efficiency and

subtracting the inductor’s power dissipation (

). The

junction temperature rise above ambient is this power

multiplied by the thermal resistance. Use the HIP5020

design and simulation software for more accurate thermal

simulations. Be sure to keep the junction temperature below

good thermal design maximized the efficiency and reliability

of the converter.

Detailed Characteristics

Charge Pump Regulator

the internal functions of the HIP5020. The charge pump

operates for input voltage levels below 9.8V and is disabled

for input voltages above 9.8V. Figure 10 shows the charge

pump operates in two regions - as a voltage doubler and as

a voltage regulator. The charge pump operates as a normal

regulation region. For input voltages above 9.8V, the charge

diode drop.

0.01

0.1

1

10

80

85

90

95

100

LOAD CURRENT (A)

0.001

FIGURE 9. EFFICIENCY vs LOAD CURRENT

75

70

C8

MIN

T

SOFT

10

5

–

V

REF

---------------

•

=

where T

SOFT

C1

V

O

•

3A

----------------------

=

2

•

HIP5020