2-14

Functional Block Diagram

R

S

PWM

ERROR

CHARGE PUMP

REGULATOR

OVER-CURRENT

+

SD

LOWER GATE

DRIVE AND

HYSTERETIC

PHASE

PWM

CURRENT

SENSOR

-

+

-

+

VIN

VCC

BOOT

PHASE

PGND

SOFT

HMI

CP+

CP-

SLOPE

VINF

FB

GND

CT

RUN

AMP

PROTECTION

OVLD

20

µA

12pF

+

-

∑

OSCILLATOR

PWM

LATCH

SLOPE

GENERATOR

MODE

CONTROL

LOGIC

SOFT-

START

REFERENCE

1.26V

+

∆

-

∆

-

+

-

+

UPPER GATE

DRIVE

LOGIC

Pin Description

PIN NO

DESIGNATOR

FUNCTION

DESCRIPTION

1, 2, 3

VIN

Input Voltage

Connection to the power source (Battery). Operates from 4.5VDC to 18VDC.

4, 5, 27, 28

PHASE

Switch Node

Connect to output Inductor.

6, 7, 8, 9, 20,

21, 22, 23

PGND

Power Ground

Power Return and thermal interface. Solder these pins to a large copper ground plane.

10

GND

Signal Ground

Connect to the output load return.

11

FB

Voltage Sense

A divider network scales the output voltage to 1.26VDC.

12

VINF

Filtered Input

13

HMI

Hysteretic Current

A resistor to the HMI pin sets the peak inductor current level during hysteretic mode.

14

SLOPE

Ramp Set

A capacitor to ground sets the compensation ramp for current mode control.

15

CT

Frequency Set

A capacitor to ground sets the oscillator frequency.

16

BOOT

Bootstrap Bias

A capacitor to Phase pin stores energy for the upper MOSFET drive.

17

VCC

Bias Voltage

Output of charge pump regulator. Use bypass capacitor to ground.

18

CP+

Charge Pump

Capacitor

Connect a capacitor between these pins for the charge pump to generate bias power. The

internal charge pump inverter is synchronized to the oscillator.

19

CP-

24

OVLD

Over-Load

A high level on this pin signals activation of the current limit protection.

25

SOFT

Soft Start

A capacitor to ground sets the soft start interval.

26

SD

Shutdown

A low level suspends operation for a low-dissipation shutdown mode.

HIP5020