UPC8100 datasheet(3/16 Pages) NEC

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µPC8100GR

Data Sheet P10817EJ3V0DS00

PIN EXPLANATION

GND

0.0

–

RF bypass

–

1.1

RF input

–

0.9

Peaking out

–

0.12

Power-save pin

0 to 4.5

–

for

downconverter

Power-save pin

0 to 4.5

–

for

upconverter

7VCC for

2.7 to 4.5

–

upconverter

RF output

same as

–

VCC through

intactor

GND

0.0

–

REG.

ASSIGNMENT

APPLIED

PIN VOLTAGE

FUNCTION AND APPLICATION

EQUIVALENT CIRCUIT

NO.

VOLTAGE (V)

(V)

Ground for downconverter.

Must be connected to the system ground

with minimum inductance. Ground pat-

tern on the board should be formed as

wide as possible.

(Track length should be kept as short as

possible.)

Bypass of RF input for downconverter.

This pin is RF input for downconverter

designed as double balanced mixer.

This high-impedance input should be

matched with external chip inductor. (eg

4.7 nH).

Open emitter pin of low noise amplifier.

Grounded with capacitor (eg 3 pF) and

Ω) serially.

This pin can control downconverter’s

ON/OFF operation with bias as follows;

Bias: V

Operation

VPS

≥1.8

0 to 1.0

OFF

This pin can control upconverter’s ON/

OFF operation with bias as follows;

Bias: V

Operation

VPS

≥1.8

0 to 1.0

OFF

Supply voltage for upconverter.

Must be connected bypass capacitor

(e.g 1 000 pF) to minimize ground im-

pedance.

F output from upconverter.

Connect the VCC through inductor (eg 15

nH).

Ground for RF amplifier of upconverter.

REG.

VCC

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