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AN2984 Datasheet(PDF) 3 Page - STMicroelectronics

Part # AN2984
Description  Minimizing the SET-related effects
PDF  8 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2984 Datasheet(HTML) 3 Page - STMicroelectronics

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AN2984
Doc ID 15690 Rev 1
3/8
to the device terminals. As some tantalum capacitors may permanently fail when subjected
to high charge-up surge currents, it is recommended to decouple them with 470 nF
polyester capacitors.
As the RHFL4913A adjustable voltage regulator is manufactured with very high speed
bipolar technology (6 GHz fT transistors), the PCB layout must be designed with exceptional
care, with very low inductance and low mutually coupling lines. Otherwise, high frequency
parasitic signals may be picked up by the device resulting in system self-oscillation. The
benefit is an SVR performance extended to far higher frequencies.
In order to replace a standard 3-terminal industry device, fixed voltage versions are
available.
A separate Kelvin voltage sensing line provides the ADJ pin with exact load “high potential”
information. But variable remote load current consumption induces variable Iq current (Iq is
roughly the IOUT current divided by the hFE of the internal PNP series power element) routed
through the parasitic series line RW2 resistor. To compensate for this parasitic voltage, an
RW1 resistor can be introduced to provide the necessary compensating voltage signal to
the ADJ pin, as shown in Figure 3.
In the case of an FPGA power supply, as these devices are very sensitive to VDD transients
beyond a small percentage of their nominal supply voltage (usually 1.5 V), special attention
must be taken to mitigate possible heavy-ion disturbances. The worst case heavy-ion effect
can be summarized as the following: the RHFL4913A internal control loop being cut
(opened) or short-circuited for a sub-microsecond duration. During such an event, the
RHFL4913A die power element can either provide excessive current or current supply
stoppage to the output (VOUT) for a duration of about one microsecond, after which time the
voltage regulator smoothly recovers to nominal operation. To mitigate these “transients”, it is
recommended to firstly implement the PCB layout using the following notes:
●
Minimizing series/parallel parasitic inductances of the PC path;
●
Using a low ESR 47 µF tantalum VOUT filtering capacitor with a 470 nF ceramic
capacitor in parallel with the former (to reduce dynamic ESR);
With this implementation, the ELDO simulated worst transient case shows no more than a
90 mV deviation from the nominal line voltage value.
Figure 3.
Application schematic for remote load operation



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