AN2984

Mitigation technique for SET

Doc ID 15690 Rev 1

5/8

Each of the two options has its own advantages and drawbacks. In the scheme shown in

Figure 4, as the R resistor is located between the voltage regulation output and the output

voltage setting resistors, the regulation - especially with the load - is expected to be much

better and thus the output voltage more precise compared to the second option; the latter

option should have superior SET immunity.

For both configurations, the characteristics of the transients can be summarized as follows:

1.

In many of the SETs observed, both short (< 100 nsec) and long-duration (max 2 sec)

pulses are present;

2.

SET cross-section increases with the LET, as expected;

3.

SETs associated to the highest LET are those with the longest transients (provided the

other conditions are the same);

4.

140 mV, using high-quality, low-ESR, low-ESL capacitors, (i.e., ceramic or tantalum);

5.

The short-duration pulses are mostly dependent on the ESL of the capacitors used,

and also dependent on the stray inductances. Therefore, they cannot be suppressed by

simply increasing the cap value. The only way to minimize them is with an action at

board level.

6.

In the scheme of Figure 4, all long-duration pulses can be suppressed by adding a

capacitor of at least 60 µF before the filter.

Even the SET cross-section is limited, at least for LET up to 53 Mev*cm²/mg, as shown in

Figure 6.

Figure 5.

Local feedback configuration

AM07812v1

V

IN

0.2

Ω

V

OUT

+

_

15µF

100nF

0.1

Ω

220µF

R1

R2

Adj

V

I

V

O

RHFL4913A

100nF

C

OUT