Mitigation technique for SET

AN2984

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Doc ID 15690 Rev 1

1

Mitigation technique for SET

As we know, the characteristics of the voltage transient on the output of a voltage regulator,

consequent to the transfer of energy related to an ion strike with the silicon, is a critical issue

in space applications. Large undershoot can cause erratic operations in memories and

microprocessors, while overshoot of an excessive amplitude can lead to the degradation - or

even the destruction - of CMOS devices. For example, for most FPGA the recommended

operating voltage is 1.5 V with 1.6 V the maximum limit (in some applications it is restricted

to 1.575 V to maintain a further safety margin). The latter applies to both static and dynamic

operating conditions.

The recommendations in this application note are based on the outcomes of an

experimental analysis conducted at Texas A&M University (Cyclotron Single Event Effects

Test facility on device behavior in a heavy ion environment). For more information please

refer to “SEE test report V3.0 - Heavy Ion SEE test of RHFL4913A from STMicroelectronics

with SET mitigation circuitry”, issued by NASA on November 18th, 2006.

During these experiments, the configurations, illustrated in Figure 4 and Figure 5, were

found capable of reducing the SET transient's characteristics on the voltage regulator output

at a level acceptable for most critical applications, e.g. FPGA supply.

Figure 4.

Baseline bias configuration with remote feedback

V

IN

R1

0.2

Ω

V

OUT

+

_

0.1

Ω

15µF

100nF

100nF

220µF

R2

Adj

RHFL4913A

C

OUT

AM07811v1