DocID024464

Rev 2

21/27

AN4287

ECC logic test

5

ECC logic test

5.1

Overview

This section describes the required information on how to develop the software for such

ECC logic test.

The goal is to ensure high coverage of the ECC logic faults with minimum performance

penalty to customer’s application. Thus, the performance penalty must be less than 2% (e.g.

the test time should be less than 200

μs considering a FTTI of 10 ms).

The SPC564A7x/SPC564A80 FLASH memory has a UTEST (user-test) mode ECC logic

check feature which can be utilized for this ECC logic test. A data pattern with walking 0

through data and ECC parity bits can be applied during the ECC logic check procedure to

achieve high fault coverage of the ECC logic and fast execution.

5.2

Data pattern – Walking 0

To reach the needed performances the use of the data pattern with walking 0 through data

and ECC parity bits must be used. Table 1 shows the data pattern.

It is important to note that for double word data = 0xFFFF_FFFF_FFFF_FFFF, the correct

ECC check bits should be 0xFF. Therefore, every data vector in the data pattern in Table 1,

except the last one, contains a single-bit ECC error and will result in a single-bit correction.

Table 1. Data pattern used by the ECC logic test

Data vector number

8-bit ECC parity bits

64-bit data bits

0

0xFF

0xFFFF_FFFF_FFFF_FFFE

1

0xFF

0xFFFF_FFFF_FFFF_FFFD

2

0xFF

0xFFFF_FFFF_FFFF_FFFB

3

0xFF

0xFFFF_FFFF_FFFF_FFF7

4

0xFF

0xFFFF_FFFF_FFFF_FFEF

5

0xFF

0xFFFF_FFFF_FFFF_FFDF

6

0xFF

0xFFFF_FFFF_FFFF_FFBF

7

0xFF

0xFFFF_FFFF_FFFF_FF7F

……

…

62

0xFF

0xBFFF_FFFF_FFFF_FFFF

63

0xFF

0x7FFF_FFFF_FFFF_FFFF

64

0xFE

0xFFFF_FFFF_FFFF_FFFF

65

0xFD

0xFFFF_FFFF_FFFF_FFFF

……

…

71

0x7F

0xFFFF_FFFF_FFFF_FFFF

72

0xFF

0xFFFF_FFFF_FFFF_FFFF