AN3324 datasheet(19/37 Pages) STMICROELECTRONICS

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AN3324

Module software requirements for non applicative peripherals

Doc ID 18311 Rev 2

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registers have to be configure (NCF_CFG0, NCFS_CFG0, NCF_TOE0, etc.). Loss of lock

signals from FMPLL_0 and FMPLL_1 provide the FCCU “Non-Critical Fault” inputs 2 and 3.

Note:

The RGM and FCCU configuration includes the reaction in case of FMPLL loss of lock. This

reaction is application-dependent.

3.9

Internal RC Oscillator (IRCOSC)

User has to verify the availability and frequency of the internal RC oscillator and for this

reason the frequency meter of the CMU0 (see Section 3.7: Clock Monitor Unit (CMU)) must

be exploited.

User has to use this feature to measure the RC oscillator frequency using the external

oscillator clock as known one and compare it to the expected one (16MHz(d)).

Note:

The reference clock is always the XOSC. The measure starts when CMU_CSR[SFM] is set.

The measurement duration is given by the CMU_MDR register in terms of IRC clock cycles

with a width of 20 bits. The SFM bit is cleared by the hardware after the frequency

measurement is done and the count is loaded in the CMU_FDR.

The frequency FRC can be derived from the value loaded in the CMU_FDR register (FRC =

(FOSC × MD) / n) where n is the value in CMU_FDR register and MD is the value in

CMU_MDR.

Note:

Safety related modules which work on the RC clock are: FCCU and SWT. In case of RC

clock failure, these modules stop working.

3.10

Flash memory

To support the detection of dormant faults in the entire memory array and addressing logic,

user must execute array integrity self check (see Section 3.10.1: Array integrity self check

procedure).

This BIST is based on functionality built into the Flash control logic. It calculates a MISR

signature over the array content and thus validates the content of the array as well as the

decoder logic. The calculated MISR value is dependent on the array content and must be

validated by application software.

For self check during boot, user has to do the array integrity check over the entire area

except over the sectors used for EEPROM (Electrically Erasable Programmable Read Only

Memory) emulation as only one of the sectors used for EEPROM contains valid data and

that the data in this sector varies during ECU (Electronic Control Unit) life time.

Note:

This BIST must be started by application software; its result must be validated by reading

the corresponding registers in the Flash Controller after it has been finished. Refer to the

“Array integrity self check” section in the “Flash memory” chapter of RM0032 (see B.1:

Reference documents in Appendix B) for detailed informations about this BIST.

The internal RC oscillator nominal frequency is 16 MHz, but a post trim accuracy of ±6% overvoltage and

temperature must be taken into account.

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