AN3324 datasheet(31/37 Pages) STMICROELECTRONICS

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AN3324

CPU core initialization

Doc ID 18311 Rev 2

31/37

tlbwe

# Write the entry to the TLB

#table 4

....

mtspr mas3,r5

# mtspr MAS3,r5

tlbwe

# Write the entry to the TLB

#table 5

....

tlbwe

# Write the entry to the TLB

se_isync

##--------- SET UP MMU (END)--------------------------------------------

##---------

Initialise Registers ---------------------

e_li r1, 5

....

e_li r31, 5

# reset of selected registers

mtcrf 0xFF,r31

mtspr 285,r31 #TBU

.... mtspr 603,r31

##---------

end Initialise Registers ---------------------

##------- Initialise SRAM ECC -----------------------------------------------

# Doing this in halves for 128k SRAM to allow for WDOG service at

# the half-way point.

# Base Address of the internal SRAM

e_lis

r5, _SRAM_BASE_ADDR@h

e_or2i

r5, _SRAM_BASE_ADDR@l

# Store number of 128Byte (32GPRs) segments in Counter

e_lis

r6, _SRAM_SIZE@h

# Initialize r6 to size of SRAM (Bytes)

e_or2i

r6, _SRAM_SIZE@l

e_srwi

r6, r6, 0x3

# Divide SRAM size by 8 (half SRAM size in words)

mtctr

# Move to counter for use with "bdnz"

# Fill SRAM with known values not registers ###############

# Never write content of uninitialised registers to SRAM ####

sram_loop1:

e_lis

r0,0x0

e_stw

r0,0x0(r5)

# Write all 32 registers to SRAM

e_addi

r5,r5,4

# Increment the RAM pointer to next 128byte

e_bdnz

sram_loop1

# Loop for all of SRAM

# Service the watchdog now (doing the entire SRAM init is too long)

e_lis

r1,0xfff3

e_or2i

r1,0x8010

e_li

r2,0xA602# SR sequence value 1

se_stw

r2,0x0(r1)

e_li

r2,0xB480# SR sequence value 2

se_stw

r2,0x0(r1)

# Finish initializing SRAM

mtctr

# r6 still contains half the SRAM size in words

sram_loop2:

e_lis

r0,0x0

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