AN3324 datasheet(20/37 Pages) STMICROELECTRONICS

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AN3324

Module software requirements for non applicative peripherals

Doc ID 18311 Rev 2

20/37

3.10.1

Array integrity self check procedure

Array integrity is checked using a pre-defined address sequence (based on UT0[AIS]), and

this operation is executed on selected blocks. The data to be read is customer specific, thus

a customer can provide user code into the Flash and the correct MISR value is calculated.

The customer is free to provide any random or non-random code, and a valid MISR

signature is calculated. Once the operation is completed, the results of the reads can be

checked by reading the MISR value, to determine if an incorrect read or ECC (Error

Correction Code

) detection was noted. Array integrity is controlled by the system clock, and it

is required that the Read Wait States and Address Pipelined control registers in the BIU

(Bus Interface Unit) be set to match the user defined frequency being used.

Caution:

While array integrity is being executed, Flash memory array access through the BIU should

not be requested.

The array integrity check consists of the following sequence of events:

Enable UTest mode.

Select the block, or blocks to receive array integrity check by writing ones to the

appropriate registers in LMS or HBS registers.

Caution:

Locked blocks can be tested with array integrity if selected in LMS and HBS. It is not

possible to do UTest operations on the shadow block.

If desired, set the UT0[AIS] bit to 1 for sequential addressing only.

Caution:

For normal integrity checks of the Flash memory, sequential addressing is recommended. If

it is required to more fully check the read path (in a diagnostic mode) completely, it is

recommended that AIS be left at 0, to use the address sequence that checks the read path

fully, and examine read transitions. This sequence takes more time.

Seed the MISR UM0 through UM4 with desired values.

Set the UT0[AIE] bit.

If desired, the array integrity operation may be aborted prior to UT0[AID] going

high. This may be done by clearing the UT0[AIE] bit and then continuing with the

next step. It should be noted that in the event of an aborted array integrity check

the MISR registers contains a signature for the portion of the operation that was

completed prior to the abort, and it is not deterministic. Prior to doing another

array integrity operation, the UM0, UM1, UM2 and UM3 registers may need to be

initialized to the desired seed value by doing register writes.

Wait until the UT0[AID] bit goes high.

Read values in the MISR registers (UM0 through UM4) to ensure correct signature.

Write a logic 0 to the UT0[AIE] bit.

If the Flash contents change, the MISRs are different: for this reason user should store

MISR value (used by self check at boot) in a separate Flash block that is unselected during

MISR calculation.

Note:

This test does have some coverage on unselected sectors like sector_eeprom, since the

array integrity check always goes through the entire Flash array (but only accumulate MISRs

for selected sectors). Therefore, the array integrity check signals any ECC error in

unselected sectors.

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