DocID023502 Rev 2

11/30

AN4146

Demonstration board and accessories

1.5.2

Clock management

Clock management is an important topic since all of the devices involved have their own

clock.

Figure 9. Clock management - block diagram subsection

The processor device needs two clocks: one for its digital core and one for the PDM (a

register bit allows selecting the ratio between the two clocks). The microphones and the

PDM interface need the same clock while the processor core clock is fed with a quadruple of

such clock. The core clock can be provided to the processor through the STEVAL-

CCA035V1, 12.288 MHz on pin 15, or thanks to an onboard 11.2896 MHz oscillator, the

selector S1 (R82-R83) is used to select one of these two clocks. The choice of the

•

12.288 MHz: Fs = 12.288/64 = 192 kHz

•

11.2896 MHz: Fs = 11.2896/64 = 176.4 kHz

The clock for the microphones and PDM interface is generated thanks to the PLL enabling

the device microphone mode (refer to the STA321MP datasheet) and exported thanks to the

clock-out (pin 25). The PDM interface is internally clocked by enabling one bit of a dedicated

device register. If the microphone mode is not enabled, the external flip-flop is used as a

frequency divider of the clock-out; this is for a debugging purposes only. For this reason, the

I/F_CLK pin stays open by not soldering it to R32.The clock routing is managed by the two

selectors S10, S11 called MIC_CLK_SEL on the board serigraphy. In microphone mode, the

STA321MPL

PDM Interface

11.2896MHz

Level shifter

Low

1.8V

S10

S11

S1

3.3V

3.3V

3.3V

/2

/4

Flip-flop

CK

High

3.3V

Microphones

Clock

APWlink

connector