Demonstration board and accessories

AN4146

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DocID023502 Rev 2

clock-out works exactly as the microphone clock, so it must be provided to the microphone

pins. This is done by closing the resistor R43 of the selector S11 (R42-R43). In the case of

supplying the microphones at 1.8 V, the clock provided to the microphones must be reduced

from 3.3 V to 1.8 V. The level shifter provides this scaled clock, if needed. When the user

wants to feed the microphones at 1.8 V, the resistor R42 of the selector S11 must be

soldered instead of R43 (R42-R43).The selector S10 (R40-R41) is used when the

microphone mode is not enabled, thus, for debugging purposes only. For this reason, both

of its resistors are not soldered.

1.5.3

MEMS microphones, PDM interface and level shifter

Since the STA321MP processor manages the channels separately, there is no need to set

the microphone in stereo configuration in this demonstration board. The L/R pins can be set

to either GND or VDD through the selectors S4, S5, S6, S7, S8 and S9 (respectively the

couples R38-R39, R36-R37, R46-R47, R44-R45, R48-R49 and R50-R51). By default, all

the L/R pins are connected to GND, in other words R36, R38, R44, R46, R48 and R51 are

soldered.

The processor STA321MP samples the microphone data according to the PDM interface

clock. The sampling edge can be set to both rising and falling since, in microphone mode,

the processor provides an internal PDM interface clock shifted 90º with respect to the clock-

out. Refer to the STA321MP/MPL datasheet for details.

The data output is a digital signal carrying the audio information with a PDM encoding. The

processor STA321MP is able to decode these signals and convert them into the more

connector; the PWM signals, suitably filtered, provide an analog interface (fuchsia traces in

Figure 10 on page 13).

Table 1. L/R channel selection

L/R

Clock low

Clock high

GND

Data valid

High impedance

VDD

High impedance

Data valid