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UPD17068 Datasheet(PDF) 49 Page - NEC

Part # UPD17068
Description  4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY SYNTHESIZER FOR DIGITAL TUNING SYSTEMS
PDF  341 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD17068 Datasheet(HTML) 49 Page - NEC

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µPD17068
5.6
INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP: MEMORY POINTER)
5.6.1
Index Register (IX)
(1) Format of Index Register
Fig. 5-6 shows the format of the index register.
The index register consists of 11 bits: the lower 3 bits (IXH) of 7AH of the system register, 7BH (IXM), and
7CH (IXL). The lower 2 bits (bits 2 and 1 of 7AH) are always set to 0. In operation to access the VRAM, however,
only the higher 1 bit (bit 2 of 7AH) is always set to 0. For the method of VRAM access, see Section 16.5.7.
Fig. 5-6 Format of Index Register
(2) Index register functions
The index register is used to modify data memory addresses when a data memory manipulation instruction
is executed. That is, the data memory bank, row address, and column address specified by a data memory
manipulation instruction are ORed with the contents of the index register, and the instruction is executed for
the data memory location specified by the result of OR operation.
Note, however, that address modification is enabled only when the IXE flag (bit 0 of 7FH of the system
register) is set to 1.
A dedicated instruction (INC IX) for incrementing the index register allows easy access to a data memory
location.
Address modification using the index register can be performed with all data memory manipulation
instructions.
With the instructions listed below, address modification using the index register is impossible.
Address
7AH
7BH
7CH
7EH
7FH
Index register (IX)
Memory pointer (MP)
IXH
IXM
MPH
MPL
IXL
Bit
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
Data memory
access
VRAM access
M
P
E
I
X
E
M
P
E
I
X
E
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
0
0
Register
Symbol
PSW
Program status word
(PSWORD)
Fixed
at
0
Fixed
at
0
Fixed
at
0
VRAMBANK
Row
address
Column
address
Column address
Row address
BANK
IX
IX



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