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UPD17068 Datasheet(PDF) 13 Page - NEC

Part # UPD17068
Description  4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY SYNTHESIZER FOR DIGITAL TUNING SYSTEMS
PDF  341 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD17068 Datasheet(HTML) 13 Page - NEC

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µPD17068
14.7.3
CE Reset .......................................................................................................................... 191
14.7.4
Halt State ........................................................................................................................ 191
15. SERIAL INTERFACE .................................................................................................................... 192
15.1
GENERAL ......................................................................................................................................... 192
15.2
SERIAL INTERFACE 0 ..................................................................................................................... 193
15.2.1
General ............................................................................................................................ 193
15.2.2
Clock I/O Control Block and Data I/O Control Block ................................................
194
15.2.3
Clock Control Block ....................................................................................................... 197
15.2.4
Clock Counter and Start/Stop Detection Block.........................................................
197
15.2.5
Presettable Shift Register 0 ..........................................................................................
199
15.2.6
Wait Control Block and Acknowledge Control Block ...............................................
200
15.2.7
Interrupt Control Block .................................................................................................
202
15.2.8
I2C Bus Mode ................................................................................................................... 203
15.2.9
Serial I/O Mode .............................................................................................................. 210
15.2.10
Data Write and Read Cautions .....................................................................................
214
15.2.11
Serial Interface 0 Operation..........................................................................................
215
15.2.12
State When Serial Interface 0 Is Reset .......................................................................
218
15.3
SERIAL INTERFACE 1 ..................................................................................................................... 219
15.3.1
General ............................................................................................................................
219
15.3.2
Clock I/O Control Block and Data I/O Control Block ................................................
219
15.3.3
Clock Counter ................................................................................................................. 220
15.3.4
Presettable Shift Register 1 ..........................................................................................
222
15.3.5
Wait Control Block .........................................................................................................
222
15.3.6
Serial Interface 1 Operation..........................................................................................
223
15.3.7
Data Write and Data Read Cautions ........................................................................... 226
15.3.8
Serial Interface 1 Operation..........................................................................................
227
15.3.9
State When Serial Interface 1 Is Reset .......................................................................
228
16. IMAGE DISPLAY CONTROLLER (IDC) ..................................................................................... 229
16.1
GENERAL ......................................................................................................................................... 229
16.1.1
Configuration ..................................................................................................................
229
16.1.2
IDC Functions ..................................................................................................................
230
16.2
IDC DISPLAY CONTROL BLOCK ................................................................................................... 231
16.2.1
IDC Display Control Block Control Registers .............................................................
231
16.2.2
Display Format ............................................................................................................... 233
16.2.3
Space between Characters ...........................................................................................
233
16.2.4
Screen Background Color .............................................................................................
235
16.3
IDC START POSITION CONTROL BLOCK ....................................................................................
235
16.3.1
Configuration of IDC Start Position Setting Register ...............................................
235
16.3.2
Horizontal Start Position Setting ................................................................................ 236
16.3.3
Vertical Start Position Setting .....................................................................................
237
16.4
CROM (CHARACTER ROM) ...........................................................................................................
239
16.4.1
Character Pattern Data Configuration ........................................................................
240
16.4.2
Definition of Character Pattern Data with Assembler ..............................................
242
16.5
VRAM (VIDEO RAM) ...................................................................................................................... 243
16.5.1
General ............................................................................................................................
243
16.5.2
Configuration of VRAM Data ........................................................................................
244



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