UPD17217CT datasheet(65/84 Pages) NEC

65 / 84 page

µPD17215, 17216, 17217, 17218

Resonator

Item

Conditions

MIN.

TYP.

MAX.

Unit

System Clock Oscillator Circuit Characteristics (TA = –40 to +85

°C, VDD = 2.0 to 5.5 V)

Recommended

Constants

Oscillation frequency

(fx)*

1.0

4.0

8.0

MHz

Ceramic

Oscillation

After VDD reached

stabilization time*

MIN. in oscillation

4ms

voltage range

* 1:

The oscillation frequency only indicates the oscillator characteristics.

The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode

release.

Caution:

To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line

in the above figure as follows, to avoid adverse wiring capacitance influences:

• Keep wiring length as short as possible.

• Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of

lines through which a large current flows.

• Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not ground

the capacitor to a ground pattern, through which a large current flows.

• Do not extract signals from the oscillator circuit.

External circuit example

XIN

XOUT

R 1

C 2

C 3

X IN

X OUT

UPD17217CT Datasheet(PDF) 65 Page - NEC

UPD17217CT Datasheet(HTML) 65 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL