| Electronic Components Datasheet Search |
|
AN1723 Datasheet(PDF) 14 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN1723 Datasheet(HTML) 14 Page - STMicroelectronics |
|
14 / 24 page ![]() Closing the loop AN1723 14/24 Doc ID 9553 Rev 4 Equation 17 where K is equal to 0.152. Therefore the PWM gain is also equal to: Equation 18 This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, therefore ensuring better line regulation and line transient response. In summary, the open loop gain can be written as: Equation 19 Example 1: Considering RC = 2.7 kΩ, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are: ● FP1 = 9 Hz ● FP2 = 256 kHz ● FZ1 = 2.68 kHz If L = 22 µH, COUT = 100 µF and ESR = 80 mΩ, the poles and zeroes of ALC becomes: ● FPLC = 3.39 kHz ● F0 = 19.89 kHz Finally R1 = 5.6 kΩ and R2 = 3.3 kΩ. The gain and phase bode diagrams are plotted respectively in Figure 14 and Figure 15. Figure 14. Module plot V OSCMAX V OSCMIN KV CC ⋅ () = – G PWM s () 1 K ---- const == Gs () G PWM s R 2 R 1 R 2 + ---------------------- A 0 ⋅⋅ s () A LC s () ⋅ () = AM11322v1 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |