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UPD17P228 Datasheet(PDF) 4 Page - NEC |
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UPD17P228 Datasheet(HTML) 4 Page - NEC |
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4 / 28 page  µPD17P228 4 Data Sheet U14542EJ1V0DS00 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 P0A P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) P0B P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) P0C P0D0 (D0) P0D1 (D1) P0D2 (D2) P0D3 (D3) P0D P0E0 P0E1 P0E2 P0E3 P0E RF SYSTEM REG. ALU OSC CPU Clock RESET WDOUT REM INT (VPP) VDD GND XIN (CLK) XOUT Instruction Decoder Power Supply Circuit Remote Control Divider 8-bit timer Interrupt Controller Program Counter Stack (5 levels) RAM 223 × 4 bits One Time PROM 8192 × 16 bits Basic Interval/ Watchdog Timer Remark ( ): during PROM programming mode |
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