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UPD17P228 Datasheet(PDF) 16 Page - NEC |
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UPD17P228 Datasheet(HTML) 16 Page - NEC |
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16 / 28 page ![]() µPD17P228 16 Data Sheet U14542EJ1V0DS00 System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Resonator Recommended Item Conditions MIN. TYP. MAX. Unit Constants Ceramic Oscillation frequency 1.0 4.0 8.0 MHz resonator (fX) Note 1 Oscillation After VDD reached MIN. 4 ms stabilization time Note 2 in oscillation voltage range Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: • Keep wiring length as short as possible. • Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. • Always keep the oscillator capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. • Do not extract signals from the oscillator. External circuit example Remark To select a resonator and determine oscillator constants, please evaluate the oscillation yourself or request the resonator manufacturer to evaluate it. X IN X OUT XIN XOUT R1 C2 C1 |
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