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AN2982 Datasheet(PDF) 12 Page - STMicroelectronics |
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AN2982 Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 31 page ![]() Designing the application AN2982 12/31 Doc ID 15599 Rev 1 Figure 7. Bode plot with simple compensation network: |Gloop|MAX < 35dB For example, an RC-series network is connected between the INV and COMP pin. The obtained Gloop(s) can be written as: Equation 28 A phase margin equal to 45° is obtained at Vin = 277 Vac using Ccomp=1.5 µF and Rcomp=39 kΩ. At minimum input voltage the phase margin is equal to 85°. Higher values of Ccomp or a lower value of Cout can also improve the PFC performance. Figure 8. Bode plot with enhanced compensation network: |Gloop|MAX < 35 dB and Φ margin > 45° () () () s 029623 . 0 1 1 V 020308 . 0 M 6 . 6 sC R sC 1 s G s G s G 2 rms , in comp comp comp comp loop + ⋅ ⋅ ⋅ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ Ω + = ⋅ = |
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