Test results and significant waveforms

AN3118

14/31

Doc ID 16847 Rev 2

To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitors,

after the bridge rectifier, should be minimized, maintaining compatibility with EMI filtering

needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input

current in itself, therefore reducing the effectiveness of the optimizer circuit.

In Figure 18, the detail of the waveforms at switching frequency shows the operation of the

transition mode control; once the inductor has transferred all the energy stored a falling edge

on the ZCD pin (#13) is detected and it will trigger a new on-time, by setting the gate drive

high. Once the current signal on the CS pin (#4) has reached the level programmed by the

internal multiplier circuitry according to the input mains instantaneous voltage and the error

amplifier output level, the gate drive is set low and MOSFET conduction is stopped. During

the following off-time the energy stored in the inductor is transferred into the output capacitor

and the load. At the end of the current conduction a new demagnetization will be detected

by the ZCD that will provide for a new on-time of the MOSFET.

reference.

Figure 16.

EVL6563H-250W TM PFC MOSFET

current at 100 Vac - 50 Hz - full load

Figure 17.

EVL6563H-250W TM PFC MOSFET

current at 100 Vac - 50 Hz - full load

CH1: Q1 gate voltage, CH2: Q2 gate voltage,

CH3: Q1 drain current

CH4: Q2 drain current

CH1: Q1 gate voltage, CH2: Q2 gate voltage,

CH3: Q1 drain current

CH4: Q2 drain current

Figure 18.

EVL6563H-250W TM PFC L6563H

control pins-1 at 115 Vac - 60 Hz -

full load

Figure 19.

EVL6563H-250W TM PFC L6563H

control pins-2 at 115 Vac - 60 Hz -

full load

CH1: GD - pin #15, CH2: ZCD - pin #13, CH3: CS - pin #4

CH4: MULT - pin #3

CH1: INV - pin #1, CH2: MULT - pin #3,