5

LT3473/LT3473A

3473f

Disconnect PNP Quiescent Current

SHDN Voltage to Turn-On

Disconnect PNP

CAP VOLTAGE (V)

0

0.8

1.0

1.2

30

3473 G13

0.6

0.4

10

20

535

15

25

40

0.2

0

1.4

OUTPUT CURRENT (mA)

0

0

0.1

0.3

0.4

0.5

40

80

100

0.9

3473 G14

0.2

20

60

0.6

0.7

0.8

TEMPERATURE (°C)

–50

0.50

0.60

0.65

0.70

0.75

0.80

0.85

0

50

3473 G15

0.90

0.95

1.00

0.55

100

PI FU CTIO S

CAP (Pin 1/Pin 1): Internal Output Voltage. This pin is the

Schottky cathode and disconnect PNP emitter. Connect

output capacitor here.

OUT (Pin 2/Pin 2): Output of Disconnect Circuit. Bypass

this pin with capacitor to ground.

CTRL (Pin 3/Pin 8): External Reference Pin. This pin sets

the FB voltage externally between 0V and 1.25V. Tie this

pin 1.5V or higher to use the internal 1.25V reference.

FB (Pin 4/Pin 7): Feedback Pin. Pin voltage is regulated to

1.25V if internal reference is used or to the CTRL pin

voltage if the CTRL pin voltage is between 0V and 1.25V.

Connect the feedback resistor divider to this pin. The

output voltage is regulated to:

VV

R

R

OUT

REF

=+

⎛

⎝

⎜

⎞

⎠

⎟

•

2

1

1

PGOOD (Pin 5/Pin 9): Power Good Output. Open collector

logic output that starts to sink current when FB reaches

within 100mV of the reference voltage.

SHDN (Pin 6/Pin 10): Shutdown Pin. Connect to 1.4V or

higher to enable device; 0.2V or less to disable device. Also

functions as soft-start. Use RC filter as shown in Figure 4.

bypassed with a X5R or X7R type ceramic capacitor.

SW (Pin 8/Pin 12): Switch Pin. Connect inductor here.

Minimize the metal trace area connected to the pin to

minimize EMI.

Exposed Pad (Pin 9/Pin 13): Ground. Solder directly to

PCB ground plane through multiple vias under the pack-

age for optimum thermal performance.

LT3473A Only

NB1 (Pin 3): NPN1 Base.

NE1 (Pin 4): NPN1 Emitter.

NB2 (Pin 5): NPN2 Base.

NE2 (Pin 6): NPN2 Emitter.

(LT3473/LT3473A)