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LTC3427 Datasheet(PDF) 5 Page - Linear Technology |
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LTC3427 Datasheet(HTML) 5 Page - Linear Technology |
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5 / 12 page ![]() 5 LTC3427 3427fa BLOCK DIAGRA Σ + – + IZERO COMP VOUT 1.8V TO 5.25V GAIN ERROR AMPLIFIER CURRENT SENSE 1.24V 1V BULK CONTROL SIGNALS L1 4.7 µH OPTIONAL VIN ANTIRING SHDN SHDN PWM LOGIC AND DRIVERS START-UP SOFT-START SHUTDOWN AND VBIAS THERMAL SHUTDOWN SLOPE COMPENSATION OSCILLATOR REFERENCE PWM COMP ILIM REF + + – + 1.24V 4 VIN 3 SW VOUT 1 6 FB R1 COUT 4.7 µF R2 5 GND 3427 BD 2 EXPOSED PAD 7 CIN 2.2 µF VIN 1.8V TO 5V SW (Pin 1): Switch Pin for the Inductor Connection. Minimize trace length between SW and the inductor. For discontinuous inductor current, an internal 200 Ω imped- ance is connected from SW to VIN to eliminate high frequency ringing, reducing EMI radiation. GND (Pin 2): Signal and Power Ground. Provide a short, direct PCB path between GND and the (–) side of the input and output capacitor(s). VIN (Pin 3): Input Supply Voltage. Connect VIN to the input supply and decouple with a 2.2 µF or larger ceramic capacitor as close to VIN as possible. SHDN (Pin 4): Shutdown Input. Less than 350mV on SHDN shuts down the LTC3427. Placing 1V or more on SHDN enables the LTC3427. FB (Pin 5): Feedback Input to the Error Amplifier. Connect resistor divider tap to this pin. Referring to the Block Diagram, VOUT can be adjusted from 1.8V to 5.25V by: VV R R OUT =+ ⎛ ⎝⎜ ⎞ ⎠⎟ 124 1 1 2 .• VOUT (Pin 6): Output Voltage Sense Input and Drain of the Internal Synchronous Rectifier MOSFET. Driver bias is derived from VOUT. PCB trace length from VOUT to the output filter capacitor(s) should be as short and wide as possible. Exposed Pad (Pin 7): Ground for the LTC3427. This pin must be soldered to the PCB ground plane for electrical connection and rated thermal performance. PI FU CTIO S |
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