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AN1812 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN1812 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 34 page ![]() 3 Timing diagram AN1812 6/34 3 Timing diagram Figure 3 shows the overall operation of the ADC. Initially the capacitor is in the reset state (M1- ON and M2- OFF), the op-amp output Vout is at V1 and so, the output of both comparators, Comp1 and Comp2 is HIGH. Capacitor charging can be started by switching M1 - OFF and M2 - ON. When the charging starts, Vout rises. When Vout becomes greater than V2, a falling edge occurs on Comp1. This causes an input capture at pin PB2 and software reads the timer value T2. When Vout becomes greater than V3, a falling edge occurs on Comp2. Again this causes an input capture at pin PB0 and software reads the timer value T3. The capacitor is discharged by switching M1 - ON and M2- OFF. After this, the ADC can be kept in reset condition by switching M1 - ON and M2 - OFF or we can continue repeating the same process and make more measurements. Figure 3. Timing diagram Charging Time Discharg. Time Settling Time V3 Vout V2 V1 0 Comp1 Comp2 M1 M2 T2 T3 Time (t) Tm Tm |
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