LTC1665 datasheet(8/18 Pages) LINER

8 / 18 page

LTC1665/LTC1660

166560fa

BLOCK DIAGRAM

PIN FUNCTIONS

GND (Pin 1): System Ground.

VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Volt-

age Outputs. The output range is

0to

255

256

⎛

⎝⎜

⎞

⎠⎟

VREF for the LTC1665

0to

1023

1024

⎛

⎝⎜

⎞

⎠⎟

VREF for the LTC1660

REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

DIN into the register. When CS/LD is pulled high, SCK is

disabled and data is loaded from the shift register into the

specified DAC register(s), updating the analog output(s).

CMOS and TTL compatible.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL

compatible.

DIN (Pin 9): Serial Interface Data Input. Data on the DIN

pin is shifted into the 16-bit register on the rising edge of

SCK. CMOS and TTL compatible.

DOUT (Pin 10): Serial Interface Data Output. Data appears

on DOUT 16 positive SCK edges after being applied to DIN.

May be tied to DIN of another LTC1665/LTC1660 for daisy-

chain operation. CMOS and TTL compatible.

CLR (Pin 11): Asynchronous Clear Input. All internal shift

and DAC registers are cleared to zero at the falling edge of

the CLR signal, forcing the analog outputs to zero scale.

CMOS and TTL compatible.

VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

(LTC1665/LTC1660)

GND

VOUT A

VOUT B

VOUT C

VOUT D

REF

CS/LD

SCK

VCC

VOUT H

VOUT G

VOUT F

VOUT E

CLR

DOUT

DIN

166560 BD

DAC A

DAC H

DAC B

DAC G

DAC C

DAC F

DAC D

DAC E

ADDRESS

DECODER

CONTROL

LOGIC

SHIFT REGISTER

LTC1665 Datasheet(PDF) 8 Page - Linear Technology

LTC1665 Datasheet(HTML) 8 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL