AN3123

Clock source and frequency

Doc ID 16862 Rev 2

11/30

3

Clock source and frequency

The reference clock provided to the UART has a frequency ranging from 1.42 MHz to 542.72

MHz.

An auxiliary clock source can also be selected using the Auxiliary clock synthesizer

registers. These are a group of read / write registers in the Miscellaneous register block

which can be used to enable an auxiliary source clock for some of the SPEAR's internal

peripherals, including the UART. The clock synthesizer is a digital signal generator. It is used

to act as a fractional clock divider.

3.1

Clock related registers

●

In SPEAr320S the PERIPHERAL CLOCK CONFIGURE REGISTER is a R/W register

used to select the UART0 peripheral clock source. The UARTCLK_sel bit in this

register allows you to select the UART0 clock source as follows:

–

‘0’

48 MHz (default clock)

–

‘1’

UART0 Clock Synthesizer

●

In SPEAR320S the RASCFG CONTROL REGISTER and ExtControl_Reg are R/W

registers providing 6 control bits used to select the peripheral clock sources for UART1

..6 and UART_485.

–

‘0’

RAS_CLK_SYNT2

–‘1’

PCLK

●

PERIP1_CLK_ENB REGISTER is a R/W register using to enable/disable the

peripheral.

–

In SPEAr300, there is a single uart_clkenb bit which enables and disables the

UART-1 clock.

–

In SPEAr600, there are 2 clock enable bits, uart1_clkenb and uart2_clkenb which

enable and disable the UART-1 and UART-2 clock, respectively.

Table 11.

Memory map on SPEAr300

Peripheral

Start address

End address

UART1

0xD000.0000

0xD007.FFFF

UART2

0xA300.0000

0xA3FF.FFFF

UART3

0xA400.0000

0xA4FF.FFFF