DMA interface

AN3123

20/30

Doc ID 16862 Rev 2

8.2

DMA registers

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UART DMA control register is a 16-bit read/write register. The bits of this register

enable and disable the DMA for the transmit and receive FIFOs. It also changes the

DMA request outputs when an UART error interrupt is asserted.

Offset Value: ‘h048

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DMACConfiguration register is a RW register which is used to configure the

operation of the DMAC. It enables the DMAC.

Offset Value: 0x030

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DMACIntTCClear (interrupt terminal count clear) register is a WO register which is

used to clear a terminal count interrupt request.

Offset Value: 0x008

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DMACIntErrClr (interrupt error clear) REGISTER is a WO register which is used to

clear an error interrupt request.

Offset Value: 0x010

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DMACCnSrcAddr (channel n source address) register is a RW register which

contains the current source address of the data to be transferred over the n-th DMA

channel.

Offset Value: 0x100 + (n · 0x020)

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DMACCnDestAddr (channel n destination address) register is a RW register which

contains the current destination address of the data to be transferred over the n-th DMA

channel.

Offset Value: 0x104 + (n · 0x020)

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DMACCnLLI (channel n linked list item) register is a RW register which contains the

address of the next Linked List Item (LLI). If next LLI is 0, then the current LLI is last in

the chain, and the DMA channel is disabled after all DMA transfers associated with it

are completed.

Offset Value: 0x108 + (n · 0x020)

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DMACCnControl REGISTER is a RW register which contains control information

about the DMA channel n, such as transfer size, burst size and transfer width.

Offset Value: 0x10C + (n · 0x020)

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DMACCnConfiguration REGISTER is a RW register which is used to configure the

relevant DMA channel.

Offset Value: 0x110 + (n · 0x020)