AN3123

UART interrupts

Doc ID 16862 Rev 2

17/30

7.2.2

UARTTXINTR

This interrupt is asserted when one of the following events occurs:

●

If the FIFOs are enabled (FEN bit set to ‘b1 in UARTLCR_H register) and the Transmit

FIFO reaches the programmed trigger level (TXIFLSEL in UARTIFLS register). The

interrupt is then cleared by writing data to the Transmit FIFO until it becomes greater

than the trigger level, or by clearing the interrupt (writing a ‘b1 to the corresponding bit

of the UARTICR register).

●

If the FIFOs are disabled and there is no data in the transmitter single location. The

interrupt is then cleared by performing a single write to the Transmit FIFO, or by

clearing the interrupt (writing a ‘b1 to the corresponding bit of the UARTICR register).

7.2.3

UARTRTINTR

This interrupt is asserted when the Receive FIFO is not empty, and no further data is

received over a 32-bit period. The interrupt is then cleared either when the Receive FIFO

becomes empty through reading all the data (or by reading the holding register), or by

clearing the interrupt (writing a ‘b1 to the corresponding bit of the UARTICR register).

7.2.4

UARTMSINTR

It represents the modem status interrupt that is a combined interrupt of the four individual

modem status lines (nUARTRI, nUARTCTS, nUARTDCS and nUARTDSR). This interrupt is

then asserted if any of the modem status lines change.

7.2.5

UARTEINTR

This error interrupt is triggered when there is an error in the reception of the data. The

interrupt can be caused by a number of different error conditions, such as overrun, break,

parity and framing.

7.2.6

UARTINTR

It is the OR logical function of all the individual masked interrupt sources. That is, this

interrupt is asserted if any of the individual interrupts are asserted and enabled.