AN3132

Pad descriptions and configurations

Doc ID 16955 Rev 1

19/24

Figure 5.

Clock cell

All the pins of the digital cells are controlled on the basis of the configuration of the

Miscellaneous register SSTLPAD_CFG_CTR (0xFCA800F0). Refer to the User Manual for

further details.

EN

TEN

TM

A

TA

Output part

ENZI

ZI

ODTRES

ODTEN

STRB

On-die

Ω

Ω

Ω

Ω

MODEZI2V5

DDR2V5

SEP

SEN

Input part

On-die

150

Ω

150

Ω

150

Ω

150

Ω

termination

termination

PU2V5

PDNCLK2V5

PDN2V5

Pull-up and

pull-down

Pull-up and

pull-down

50 k

Ω

50 k

Ω

50 k

Ω

50 k

Ω

VDDEPAD

GNDE

GND

MODEZI2V5

DDR2V5

MODEZI2V5

DDR2V5

PUPCLK2V5

IOCLKB

IOCLK

150

150

150

150