AN3132

Pad descriptions and configurations

Doc ID 16955 Rev 1

21/24

The bit 3, bit 2 and bit 1 control respectively the pins ZPROGOUTA2V5, PROGA2V5,

PROGB2V5 for all pad data and clock cells.

The following notes apply to these three bits:

●

They are independent, but not completly uncorrelated. All 8 combinations are valid, but

are partially overlapping.

●

They are board dependent, and must be determined during the tuning phase for every

PCB type.

●

They depend on the PCB characteristic impedance and the frequency of the DDR

signals.

Bit [3], the drive mode bit, changes the output impedance of the pad and must be set in

accordance with the PCB load.

It must be set to 0 (strong mode) when the characteristic impedance of the PCB is up to 50

Ohm.

It must be set to 1 (weak mode) when the characteristic impedance of the PCB is from 50 to

70 Ohm.

Bits [2] and [1 ), prog_a and prog_b, set the “way” the internal transistors of the pad are

loaded as well as the resulting effect on the slope of the signal. These 2 bits define 4

increments of increasing capability: from 00 (slower slope) to 11 (higher slope). All

intermediate values are valid.

When you deal with high frequency signals, you should configure higher slopes to increase

the data valid window, keeping in mind that the higher the slope, the more the signal

reflection.

10

pull-down not active and pull-up not active (default)

11

pull-down not active and pull-up active

Table 5.

Pull-up and pull down settings (continued)

Bit pair value

Meaning