Pad descriptions and configurations

AN3132

20/24

Doc ID 16955 Rev 1

7.1

SSTLPAD_CFG_CTR register configuration

The pads should be configured according to the type of memory in use (DDR1 or DDR2)

In the SSTLPAD_CFG_CTR register, Bits [19:16] and bit [0] are used in conjunction with

pin DDR2_EN to configure the pads in hardware or software mode.

●

Bits [19:16] = 0000: hardware configuration mode.

In this mode, the input level of the DDR2_EN pin selects the configuration

(DDR2_EN =1 = configuration for DDR2) and DDR_PAD register [0] is don’t care.

●

Bits [19:16] = 0110: software configuration mode.

In this mode, the value of DDR_PAD register [0] selects the configuration]

(1 = configuration for DDR2) and pin DDR2_EN is don’t care.

All other combinations are not allowed.

Bit [15] is a status bit and reflects the status of the pin DDR2_EN.

All the other combinations are not allowed.

All these settings establish the value for the pin DDR2V5 of pad data and clock cells and

configure them to operate properly on the basis of the memory type attached.

Bit [14] establishes the nature of the common reference for all SSTL pads.

0 = internal reference and

1 = external reference.

It is recommended to use an external reference to improve the stability.

Bit [12] decides the nature of the clock cells: fully differential (differential) or pseudo-

differential (single ended). This bit controls the pin STRB of the pad clock cell, but only for

the pads DDR_MEM_DQS [1:0] . When in DDR1 mode the bit 12 must be set to 1 to put the

pads in single ended mode.

For the pad DDR_MEM_CLKP/N the pin STRB is blocked to 0. These pads operate in

differential mode both in DDR1 and DDR2 operating mode.

Bits [11:10] respectively control the pull-up and the pull-down of pins PDNCLKB2V5 and

PUPCLKB2V5 of the pad clock cells for the DDR_MEM_DQS[1:0] pads.See Table 5 for the

settings.

Bits [9: 8] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and

PUPCLK2V5 of the pad clock cells for the DDR_MEM_DQS[1:0] pads.See Table 5 for the

settings.

Bits [7: 6] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and

PDNCLKB2V5 of the pad clock cell for the DDR_MEM_CLKP/N pads.See Table 5 for the

settings.

Bits [5: 4] control the pull-up and the pull-down of the pins PU2V5 and PDN2V5 of all pad

data cells.See Table 5 for the settings.

Table 5.

Pull-up and pull down settings

Bit pair value

Meaning

00

pull-down active and pull-up not active

01

forbidden