AN3322 datasheet(27/38 Pages) STMICROELECTRONICS

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AN3322

Computational issues and compensation algorithms

The meter should be able to measure and correct the mains frequency fluctuation of ± 2%;

it means from 49 to 51 Hz according to the international standard. The HSI RC oscillator has

a frequency fluctuation ± 3% (even the internal HSI can be calibrated by RTC to accuracy ±

1%) over the whole temperature range (the value ± 3% is used for computation as the worst

case). If the combination of the maximum network frequency variation and maximum HSI

frequency variation is ± 5%, it means from 47.5 to 52.5 Hz. The meter must be able to adapt

to this variation and measure correctly in this range of values.

All the computation for precise timing is updated only when input voltage is higher than 50 V.

A possible voltage drop over some periods can bring a frequency detection error. The

international standards allow incorrect measurement during the period of the time when

voltage is under 80% of its nominal value.

The algorithm for the precise timer setting uses the mains zero crossing information. In

order to keep the whole number of the samples per period of the mains, the positive zero

crossing of the mains must still appear in the same position in the sampled data array (for

example: if we detect zero crossing at the 4th sample out of 44, in the next period of mains

the zero crossing must appear in the same position, it means the 4th sample out of 44). The

sample triggering timer constant must be updated to keep the zero crossing at the same

sample index. The timer constant is updated only if the zero crossing is different from the

previous one. If the difference is positive, the timer constant is updated by -1, if the

difference is negative, the timer constant is updated by +1. This negative feedback locks the

sampling frequency to the frequency of mains.

The sampling frequency difference represented by one sample (44 samples per period

of 50 Hz) is 1.16 Hz (which is 2%). If the timer setting differs from mains by less than 2%,

the difference in zero crossing position appears after many cycles of mains (the lower the

difference, the more cycles there are). If we react only by adding or subtracting value 1 from

the timer constant only when the difference is one whole sample, the frequency locking lasts

for 225 steps (over the whole range - see the beginning of this section). More than

5 s is needed to stabilize the zero crossing sample index value to less than one between

directly subsequent periods of mains. Furthermore, after that synchronization period, if the

difference is lower than one whole sample index, the update of the timer is done after the

difference appears over more periods and reaches one sample index. Typically, the lock-in

time is about 30 seconds additionally.

Reduction of the necessary time for zero crossing stabilization (synchronizes the sampling

with the mains frequency) can be done by introducing a sample index division in order to get

finer and faster zero crossing stabilization. Using this technique, the lock-in algorithm needs

1-2 seconds to fully synchronize sampling with the network.

AN3322 Datasheet(PDF) 27 Page - STMicroelectronics