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PM0044 Datasheet(PDF) 24 Page - STMicroelectronics |
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PM0044 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 162 page  Pipelined execution PM0044 24/162 Doc ID 13590 Rev 3 5.4.1 Optimized pipeline example – execution from Flash Program memory In the example shown in Table 6, the code is stored in the Flash Program memory (32-bit bus). As a result, 3 cycles are needed to fill the 96-bit prefetch buffer. At each cycle, one word is loaded and stored in F1, F2 and F3. The next fetch operation can start only when all the instructions contained in one of the Fx word are decoded. In fact, at cycle 9, the last instruction contained in F3 (SWAP A) is decoded, and a fetch operation can start to fill F3 word. Table 4. Example with conventional number of cycles Address Instruction Decode cycles Execute cycles lgth Time (cycle) 1 234567 8 9 10 11 12 13 14 0xC000 LDW X, [$50.w] 4 3 3 F1 D E E E E 0xC003 ADDW X, #20 3 3 3 F2 D D D D E E E 0xC006 LD A, [$30].w 3 3 3 F3 D D D D E E E 0xC009 …. Table 5. Legend Symbol/Color Definition FFetch D Decode stalled DDecode EExecute |
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