PM0044 datasheet(26/162 Pages) STMICROELECTRONICS

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Pipelined execution

PM0044

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Doc ID 13590 Rev 3

5.4.2

Optimize pipeline example – execution from RAM

In the example shown in Table 8, the RAM is accessed through an 8-bit bus. As a result, 12

cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and

stored in Fx. The decoding of the first word instruction can start only when the Fx word is

filled. This occurs for example till the 4th cycle, and the first instruction (NEG A) can be

decoded only at the 5th cycle.

In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6th cycle

since RAM address 10 is read during the decode stage of XOR A, $10.

Table 8.

Optimize pipeline example – execution from RAM

Add.

Cycle

10 11

14 15 16 17 18

19 20 21

0xC000

NEG A

0xC001

XOR A,

$10

0xC003

LD A, #20

0xC005

SUB

A,$1000

0xC008

INC A

0xC009

LD XL, A

0xC00A

SRL A

0xC00B

SWAP A

0xC00C

SLA $15

0xC00E

A,#$FE

Table 9.

Legend

Symbol/Color

Definition

FFetch

Fetch stalled

DDecode

Decode stalled

EExecute

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