LTC6905 datasheet(7/12 Pages) LINER

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LTC6905

6905fd

THEORY OF OPERATION

As shown in the Block Diagram, the LTC6905’s master

oscillator is controlled by the ratio of the voltage between

the V+ and SET pins and the current entering the SET pin

(IRES). The voltage on the SET pin is forced to approxi-

mately 1V below V+ by the PMOS transistor and its gate

bias voltage.

A resistor RSET, connected between the V+ and SET pins,

“locks together” the voltage (V+ – VSET) and current, IRES,

variation. This provides the LTC6905’s high precision. The

master oscillation frequency reduces to:

MHz

SET

168 5

.•

To extend the output frequency range, the master oscillator

signal is divided by 1, 2 or 4 before driving OUT (Pin 5).

The LTC6905 is optimized for use with resistors between

10k and 25k, corresponding to oscillator frequencies

between 17.225MHz and 170MHz. The divide-by value is

determined by the state of the DIV input (Pin 4). Tie DIV to

V+ or drive it to within 0.4V of V+ to select ÷1. This is the

highest frequency range, with the master output frequency

passed directly to OUT. The DIV pin may be ﬂoated or driven

to midsupply to select ÷2, the intermediate frequency

range. The lowest frequency range, ÷4, is selected by

tying DIV to GND or driving it below 0.5V. Figure 1 shows

the relationship between RSET, divider setting and output

frequency, including the overlapping frequencies.

OUTPUT FREQUENCY (MHz)

÷4 ÷2

÷1

6905 F01

110

160

Figure 1. RSET vs Output Frequency

LTC6905 Datasheet(PDF) 7 Page - Linear Technology