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PD17012 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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PD17012 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 320 page  µPD17012, 17P012 37 Data Sheet U10101EJ4V0DS Table 4-1. Data Memory Manipulation Instructions Function Instruction Operation Addition ADD ADDC Subtraction SUB SUBC Logical AND OR XOR Compare SKE SKGE SKLT SKNE Transfer MOV LD ST Judgement SKT SKF 4.3 Addressing of Data Memory Figure 4-3 shows addressing of the data memory. An address of the data memory is specified by a bank, a row address, and a column address. The row and column addresses are directly specified by using a data memory manipulation instruction. The bank is specified by the contents of the bank register. For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Addressing of Data Memory Bank register M Data memory address b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 Bank Row Address Column Address Instruction operand |
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