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PD16724 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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PD16724 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 26 page ![]() Data Sheet S16086EJ1V0DS 20 µµµµPD16724 Timing Requirements (TA = −10 to +75°°°°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PWCLK 2.3 V ≤ VDD1 < 3.0 V 20 ns 3.0 V ≤ VDD1 ≤ 3.6 V 17 ns Clock pulse high period PWCLK(H) 2.3 V ≤ VDD1 < 3.0 V 5 ns 3.0 V ≤ VDD1 ≤ 3.6 V 3 ns Clock pulse low period PWCLK(L) 2.3 V ≤ VDD1 < 3.0 V 5 ns 3.0 V ≤ VDD1 ≤ 3.6 V 3 ns Data setup time tSETUP1 0ns Data hold time tHOLD1 3ns Start pulse setup time tSETUP2 0ns Start pulse hold time tHOLD2 3ns POL21, POL22 setup time tSETUP3 0ns POL21, POL22 hold time tHOLD3 3ns STB pulse width PWSTB 1.0 µs 2CLK Last data timing tLDT 2CLK STB-CLK time tSTB-CLK STB ↑→ CLK↑ 4ns Time between STB and start pulse tSTB-STH STB ↑→ STHR (STHL) ↑ 2CLK POL-STB time tPOL-STB POL ↑ or ↓→ STB ↑ 4ns STB-POL time tSTB-POL STB ↓→ POL ↓ or ↑ 4ns STB-SRC time tSTB-SRC1 STB ↑ → SRC1 ↑ 0ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 5 5 5 5 |
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