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RM0312 Datasheet(PDF) 107 Page - STMicroelectronics |
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RM0312 Datasheet(HTML) 107 Page - STMicroelectronics |
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107 / 275 page  DocID022352 Rev 3 107/275 RM0312 16-bit general purpose timer (TIM2/TIM3) 170 17.3 TIMx time base unit The timer has a Time base unit that includes: • 16-bit up/down counter • 16-bit auto-reload register • Prescaler Figure 20. Time base unit The 16-bit counter, the prescaler and the auto-reload register can be written or read by software. The auto-reload register is composed of a preload register plus a shadow register. Writing to the auto-reload register can be done in two modes: • Auto-reload preload enabled (ARPE bit set in the TIMx_CR1 register). In this mode, when data is written to the autoreload register, it is kept in the preload register and transferred into the shadow register at the next update event (UEV). • Auto-reload preload disabled (ARPE bit cleared in the TIMx_CR1 register). In this mode, when data is written to the autoreload register it is transferred into the shadow register immediately. An update event is generated: • On a counter overflow or underflow. • By software, setting the UG bit in the TIMx_EGR register. • By an trigger event from the clock/trigger controller. With preload enabled (ARPE=1), when an update event occurs: the auto-reload shadow register is updated with the preload value (TIMx_ARR) and the buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSCR register). The update event (UEV) can be disabled by setting the UDIS bit in the TIMx_CR1 The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set. Note: Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler Auto-Reload Register 16-bit Counter CK_PSC CK_CNT TIMx_PSCR TIMx_CNTRH, CNTRL TIMx_ARRH, ARRL UEV UIF UEV Reg event Legend: Preload registers transferred to shadow registers on update control bit interrupt event (UEV) according to |
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