RM0312 datasheet(127/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of Timer A when its TI1 input rises, and the enable of

Timer B with the enable of Timer A. Refer to Figure 42 for connections. To ensure the

counters alignment, Timer A must be configured in master/slave mode (slave with respect to

TI1, master with respect to Timer B).

Configure Timer A master mode to send its Enable as trigger output (MMS=001 in the

TIMx_CR2 register).

Configure Timer A slave mode to get the input trigger from TI1 (TS=100 in the

TIMx_SMCR register).

Configure Timer A in trigger mode (SMS=110 in the TIMx_SMCR register).

Configure the Timer A in Master/Slave mode by writing MSM=’1’ (TIMx_SMCR

Configure Timer B to get the input trigger from Timer A (TS=001 in the TIMx_SMCR

Configure Timer B in trigger mode (SMS=110 in the TIMx_SMCR register).

When a rising edge occurs on TI1 (Timer A), both counters starts counting synchronously on

the internal clock and both TIF flags are set.

Note:

In this example both timers are initialized before starting (by setting their respective UG

bits). Both counters starts from 0, but you can easily insert an offset between them by

writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode

insert a delay between CNT_EN and CK_PSC on Timer A.

Figure 47. Triggering Timer A and B with Timer A TI1 input

fMASTER

Timer A-CEN = CNT_EN

Timer A-CNT

Timer A-TI1

Timer A-CK_PSC

02 03 04 05 06 07 08 09

Timer A-TIF

Timer B-CEN = CNT_EN

Timer B-CNT

Timer B-CK_PSC

02 03 04 05 06 07 08 09

Timer B-TIF

RM0312 Datasheet(PDF) 127 Page - STMicroelectronics