LTC2302 datasheet(16/20 Pages) LINER

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LTC2302/LTC2306

23026fa

APPLICATIONS INFORMATION

Internal Conversion Clock

The internal conversion clock is factory trimmed to

achieve a typical conversion time (tCONV) of 1.3μs and a

maximum conversion time of 1.6μs over the full operating

temperature range. With a minimum acquisition time of

240ns, a throughput sampling rate of 500ksps is tested

and guaranteed.

Digital Interface

The LTC2302/LTC2306 communicate via a standard

4-wire SPI compatible digital interface. The rising edge

of CONVST initiates a conversion. After the conversion

is ﬁnished, pull CONVST low to enable the serial output

(SDO). The ADC then shifts out the digital data in 2’s

complement format when operating in bipolar mode or

in straight binary format when in unipolar mode, based

on the setting of the UNI bit.

For best performance, ensure that CONVST returns low

within 40ns after the conversion starts (i.e., before the ﬁrst

bit decision) or after the conversion ends. If CONVST is

low when the conversion ends, the MSB bit will appear at

SDO at the end of the conversion and the ADC will remain

powered up.

Timing and Control

The start of a conversion is triggered by the rising edge

of CONVST. Once initiated, a new conversion cannot be

restarted until the current conversion is complete. Figures 6

and 7 show the timing diagrams for two different examples

of CONVST pulses. Example 1 (Figure 6) shows CONVST

staying HIGH after the conversion ends. If CONVST is high

after the tCONV period, the LTC2302/LTC2306 enter sleep

mode (see Sleep Mode for more details).

When CONVST returns low, the ADC wakes up and the

most signiﬁcant bit (MSB) of the output data sequence at

SDO becomes valid after the serial data bus is enabled. All

other data bits from SDO transition on the falling edge of

each SCK pulse. Conﬁguration data (DIN) is loaded into the

LTC2302/LTC2306 at SDI, starting with the ﬁrst SCK rising

edge after CONVST returns low. The S/D bit is loaded on

the ﬁrst SCK rising edge.

Example 2 (Figure 7) shows CONVST returning low be-

fore the conversion ends. In this mode, the ADC and all

internal circuitry remain powered up. When the conver-

sion is complete, the MSB of the output data sequence

at SDO becomes valid after the data bus is enabled. At

this point(tCONV 1.3μs after the rising edge of CONVST),

pulsing SCK will shift data out at SDO and load conﬁgura-

tion data (DIN) into the LTC2302/LTC2306 at SDI. The ﬁrst

SCK rising edge loads the S/D bit. SDO transitions on the

falling edge of each SCK pulse.

Figures 8 and 9 are the transfer characteristics for the

bipolar and unipolar modes. Data is output at SDO in 2’s

complement format for bipolar readings or in straight

binary for unipolar readings.

Sleep Mode

The ADC enters sleep mode when CONVST is held high

after the conversion is complete (tCONV). The supply cur-

rent decreases to 7μA in sleep mode between conversions,

thereby reducing the average power dissipation as the

sample rate decreases. For example, the LTC2302/LTC2306

draw an average of 14μA with a 1ksps sampling rate. The

LTC2302/LTC2306 power down all circuitry when in sleep

mode.

Board Layout and Bypassing

To obtain the best performance, a printed circuit board with

a solid ground plane is required. Layout for the printed

circuit board should ensure digital and analog signal lines

are separated as much as possible. Care should be taken

not to run any digital signal alongside an analog signal.

All analog inputs should be shielded by GND. VREF and

VDD should be bypassed to the ground plane as close to

the pin as possible. Maintaining a low impedance path

for the common return of these bypass capacitors is

essential to the low noise operation of the ADC. These

traces should be as wide as possible. See Figure 5 for a

suggested layout.

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