AN4467 datasheet(11/33 Pages) STMICROELECTRONICS

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DocID026156 Rev 2

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AN4467

Power supplies

1.2

Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

•

The VDD pins must be connected to VDD with external decoupling capacitors; one

single tantalum or ceramic capacitor (minimum 4.7 µF, typically 10 µF) for the package

+ one 100 nF ceramic capacitor for each VDD pin).

•

The VDDA pin must be connected to two external decoupling capacitors (100 nF

ceramic capacitor + 1 µF tantalum or ceramic capacitor).

•

The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitor must be

connected on this pin. To compensate peak consumption on Vref, the 1 µF capacitor

may be increased up to 10 µF when the sampling speed is high. When ADC or DAC is

used, VREF+ must remain between 1.8 V and VDDA. VREF+ can be grounded when ADC

and DAC are not active; this enables the user to power down an external voltage

reference.

•

Additional precautions can be taken to filter digital noise: VDDA can be connected to

VDD through a ferrite bead. In this case take care to keep a (VDDA- VDD) difference

lower than 300 mV.

Figure 2. Power supply scheme

1. VREF+ is either connected to VDDA or to VREF.

2. N is the number of VDD and VSS inputs.

AN4467 Datasheet(PDF) 11 Page - STMicroelectronics