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AN4472 Datasheet(PDF) 21 Page - STMicroelectronics |
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AN4472 Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 44 page ![]() DocID026198 Rev 1 21/44 AN4472 Hardware layout and configuration 44 Figure 14. Acquisition by Program 4, H-Bridge TX1, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively 3.4.7 Pattern Program 5 The sixth pattern stored in the SPI Flash is described in Table 18, where the output pulses are in phase and SEL is 1 for the 5-level output option. The state sequence is given in Table 18. The test conditions applied to generate the waveforms in Figure 15 and Figure 16 are: – HVP0 = + 80 V – HVP1 = + 40 V – HVM0 = - 80 V – HVM1 = - 40 V – Load: 300 pF // 100 Ω Table 18. Program 5, SEL=1 mode Frequency [MHz] Number of pulses Initial pulse PRF H-Bridge XDCR_1 PC 2.5 2 positive 300 µs TX0 XDCR_2 PC 2.5 2 negative 300 µs TX1 XDCR_3 PC 5 2 positive 300 µs TX0 XDCR_4 PC 5 2 negative 300 µs TX1 |
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