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AN4472 Datasheet(PDF) 33 Page - STMicroelectronics |
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AN4472 Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 44 page ![]() DocID026198 Rev 1 33/44 AN4472 Connectors 44 Two right-angle, 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J8, J9) are interfaced to the FPGA, with each header providing 3.3 V power, ground and eight I/O's. These headers may be used as general-purpose I/Os or to interface with the PMODs in order to enable additional user customizations. J8 and J9 are placed in close proximity (0'9" - centers) on the PCB in order to support dual PMODs. The STEVAL-IME008V1 evaluation board supports the serial peripheral interface (SPI Flash) method for configuring the FPGA. The default configuration mode (determined by pullup/pulldown resistors R17, R18, R21, and R22) is "Master Serial / SPI" mode, which allows the FPGA to be configured by the SPI Flash device. Spartan-6 devices have a dedicated four-wire JTAG port (always available to the FPGA regardless of the mode pin settings), allowing the Boundary-scan configuration method. Configuring the FPGA via Boundary-scan requires a JTAG download cable to be attached to the 14-pin 2 mm spaced keyed header J11 (to be mounted) with a ribbon cable. Resistors RN1, R41 to R44 and diode D22 must also be mounted. Jumper J13 is used to prevent FPGA programming from the configuration source. It must be open (default) to enable FPGA programming. The DONE LED (D23) on the board lights when the FPGA has successfully been configured. Table 30. FPGA PMOD connectors (J9) not mounted on the board Pin number Description Pin number Description 1 Not used 2 Not used 3 Not used 4 Not used 5 GND 6 3.3 V 7 Not used 8 Not used 9 Not used 10 Not used 11 GND 12 3.3 V Table 31. FPGA JTAG connectors (J11) not mounted on the board Pin number Description Pin number Description 1 GND 2 3.3 V 3 GND 4 TMS 5 GND 6 TCK 7 GND 8 TDO 9 GND 10 TDI 11 GND 12 Not used 13 GND 14 Not used |
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