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AN4472 Datasheet(PDF) 23 Page - STMicroelectronics |
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AN4472 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 44 page ![]() DocID026198 Rev 1 23/44 AN4472 Hardware layout and configuration 44 Figure 16. Acquisition by Program 5, zoom of Figure 15, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively 3.4.8 Pattern Program 6 The seventh pattern stored in the SPI Flash is described in Table 20, with the output pulses in phase and SEL is 0 for the 3-level output option. The state sequence is given in Table 21. The test conditions applied to generate the waveforms in Figure 17 are: – HVP0 = HVP1 = + 80 V – HVP_CW = + 40 V – HVM0 = HVM1 = - 80 V – HVM_CW = - 40 V – Load: 300 pF // 100 Ω Table 20. Program 6, SEL=0 mode Frequency [MHz] Number of pulses Initial pulse PRF H-Bridge XDCR_1 PW -CW 2.5 10 (PW) + 10 (CW) positive 300 µs TX0 & TX1, CW (0.5 A) XDCR_2 PW -CW 2.5 10 (PW) + 10 (CW) negative 300 µs TX0 & TX1, CW (0.5 A) XDCR_3 PW -CW 5 10 (PW) + 10 (CW) positive 300 µs TX0 & TX1, CW (0.5 A) XDCR_4 PW -CW 5 10 (PW) + 10 (CW) negative 300 µs TX0 & TX1, CW (0.5 A) |
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