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UPD72001C Datasheet(PDF) 31 Page - NEC |
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UPD72001C Datasheet(HTML) 31 Page - NEC |
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31 / 40 page ![]() µPD72001-11, 72001-A8 31 E/S Timing CTSA/B, DCDA/B, SYNCA/B INT tWML tWMH tDMIQ SYNC Input Timing (external synchronization mode) SYNCA/B Note tSSYRC STRXCA/B TRXCA/B Last Bit of SYNC Character 1st Bit of Data Character Note SYNCA/B input must be cleared to “0” at the rising edge of RXC two clock cycles after the last bit of the SYNC character. XI1 Input Timing XI1 tCYX RESET Pulse RESET tWRSL |
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