6

LT1512

current amplifier is set to a fixed gain of – 12.5 which

provides a – 100mV current limit sense voltage.

The error signal developed at the amplifier output is

brought out externally and is used for frequency compen-

sation. During normal regulator operation this pin sits at a

voltage between 1V (low output current) and 1.9V (high

an idle mode.

The LT1512 is an IC battery charger chip specifically opti-

mized to use the SEPIC converter topology. The SEPIC

topology has unique advantages for battery charging. It will

operate with input voltages above, equal to or below the

battery voltage, has no path for battery discharge when

turned off and eliminates the snubber losses of flyback

designs. It also has a current sense point that is ground

referred and need not be connected directly to the battery.

The two inductors shown are actually just two identical

windings on one inductor core, although two separate

inductors can be used.

A current sense voltage is generated with respect to ground

across R3 in Figure 1. The average current through R3 is

always identical to the current delivered to the battery. The

LT1512 current limit loop will servo the voltage across R3 to

– 100mV when the battery voltage is below the voltage limit

set by the output divider R1/R2. Constant current charging

is therefore set at 100mV/R3. R4 and C4 filter the current

and R2 form a divider for battery voltage sensing and set the

battery float voltage. The suggested value for R2 is 12.4k. R1

is calculated from:

R

RV

RA

BAT

1

2

1 245

1 245

2 0 3

=

+µ

(– .

)

.( .

)

0.3

µA = typical FB pin bias current

A value of 12.4k for R2 sets divider current at 100

µA. This is

a constant drain on the battery when power to the charger is

off. If this drain is too high, R2 can be increased to 41.2k,

reducing divider current to 30

µA. This introduces an addi-

tional uncorrectable error to the constant voltage float mode

of about

±0.5% as calculated by:

V

Error =

0.15 A(R1)(R2)

1.245(R1+ R2)

BAT

±µ

±0.15µA = expected variation in FB bias current around

the nominal 0.3

µA typical value.

to variations in bias current would be

±0.42%.

A second option is to disconnect the voltage divider with a

small NMOS transistor as shown in Figure 3. To ensure

at its lowest operating point of 2.4V), the FET gate is driven

wth a peak detected voltage via D2. Note that there are two

connections for D2. The L1 A connection must be used if the

voltage divider is set for less than 3.5V (fully charged

battery). Gate drive is equal to battery voltage

plus input

voltage. The disadvantage of this connection is that Q1 will

down via the S/S pin. The L1 B connection allows Q1 to turn

on-state for fully charged battery voltages less than 3.5V. Do

not substitute for Q1 unless the new device has adequate

C6 filters the gate drive and R5 pulls the gate low when

switching stops.

Disconnecting the divider leaves only D1 diode leakage as a

battery drain. See Diode Selection for a discussion of diode

leakage.