6

LTC1174

LTC1174-3.3/LTC1174-5

FU CTIO AL DIAGRA

(Pin 1 connection shown for LTC1174-3.3 and LTC1174-5, changes create LTC1174)

–

+

–

+

–

+

0.1

Ω

RESET

1174 BD

1.25V

REFERENCE

Q

GND 4

5

SW

1

7

–

+

A1

×

R1*

31.5k

SET

6

3

SHUTDOWN

8

SLEEP

–

+

A3

A4

A5

* R1 = 51k FOR LTC1174-3.3

R1 = 93.5k FOR LTC1174-5

A2

The LTC1174 uses a constant off-time architecture to

switch its internal P-channel power MOSFET. The off-time

is set by an internal timing capacitor and the operating

The output voltage is set by an internal resistive divider

(LTC1174-3.3 and LTC1174-5) or an external divider re-

compares the divided output voltage to a reference voltage

of 1.25V.

To optimize efficiency, the LTC1174 automatically switches

between continuous and Burst Mode

age comparator is the primary control element when the

device is in Burst Mode operation, while the current com-

parator controls the output voltage in continuous mode.

During the switch“ON” time, switch current flows through

the 0.1

Ω sense resistor. When this current reaches the

threshold of the current comparator A2, its output signal will

change state, setting the flip-flop and turning the switch off.

Burst Mode

which resets the flip-flop and causes the switch to turn on

again. Also, the timing capacitor is recharged. The inductor

current will again ramp up until the current comparator A2

trips. The cycle then repeats.

When the load is relatively light, the LTC1174 automatically

goes into Burst Mode operation. The current mode loop is

interrupted when the output voltage reaches the desired

regulated value. The hysteretic voltage comparator A1 trips

the switch and causing the timing capacitor to discharge.

generated.

In sleep mode, the LTC1174 is in standby and the load

current is supplied by the output capacitor. All unused